? semiconductor components industries, llc, 2012 july, 2012 ? rev. 0 1 publication order number: nvd6824nl/d nvd6824nl power mosfet 100 v, 20 m , 41 a, single n ? channel features ? low r ds(on) to minimize conduction losses ? high current capability ? avalanche energy specified ? aec ? q101 qualified ? these devices are pb ? free, halogen free/bfr free and are rohs compliant maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss 100 v gate ? to ? source voltage v gs 20 v continuous drain cur- rent r jc (note 1) steady state t c = 25 c i d 41 a t c = 100 c 29 power dissipation r jc (note 1) t c = 25 c p d 90 w t c = 100 c 45 continuous drain cur- rent r ja (notes 1 & 2) steady state t a = 25 c i d 8.5 a t a = 100 c 6.0 power dissipation r ja (notes 1 & 2) t a = 25 c p d 3.9 w t a = 100 c 1.9 pulsed drain current t a = 25 c, t p = 10 s i dm 238 a current limited by package (note 3) t a = 25 c i dmaxpkg 60 a operating junction and storage temperature t j , t stg ? 55 to 175 c source current (body diode) i s 41 a single pulse drain ? to ? source avalanche energy (t j = 25 c, v gs = 10 v, i l(pk) = 40 a, l = 0.1 mh, r g = 25 ) e as 80 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. thermal resistance maximum ratings parameter symbol value unit junction ? to ? case ? steady state (drain) r jc 1.7 c/w junction ? to ? ambient ? steady state (note 2) r ja 39 1. the entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. surface ? mounted on fr4 board using a 650 mm 2 , 2 oz. cu pad. 3. continuous dc current rating. maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle. dpak case 369c style 2 marking diagrams & pin assignment 100 v 20 m @ 10 v r ds(on) 41 a i d v (br)dss 23 m @ 4.5 v http://onsemi.com 1 2 3 4 n ? channel d s g 1 gate 2 drain 3 source 4 drain yww 68 24lg y = year ww = work week 6824l = device code g = pb ? free package device package shipping ? ordering information NVD6824NLT4G dpak (pb ? free) 2500/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d.
nvd6824nl http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 100 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss /t j 92 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 100 v t j = 25 c 1.0 a t j = 125 c 100 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 4) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.5 2.5 v negative threshold temperature coefficient v gs(th) /t j ? 6.5 mv/ c drain ? to ? source on resistance r ds(on) v gs = 10 v, i d = 20 a 16.5 20 m v gs = 4.5 v, i d = 20 a 18.5 23 forward transconductance gfs v ds = 15 v, i d = 20 a 18 s charges, capacitances and gate resistances input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 25 v 3468 pf output capacitance c oss 187 reverse transfer capacitance c rss 133 total gate charge q g(tot) v gs = 4.5 v, v ds = 80 v, i d = 20 a 34 nc v gs = 10 v, v ds = 80 v, i d = 20 a 66 threshold gate charge q g(th) v gs = 10 v, v ds = 80 v, i d = 20 a 3.5 gate ? to ? source charge q gs 9.0 gate ? to ? drain charge q gd 18 switching characteristics (note 5) turn ? on delay time t d(on) v gs = 10 v, v dd = 80 v, i d = 20 a, r g = 2.5 15 ns rise time t r 55 turn ? off delay time t d(off) 31 fall time t f 42 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 20 a t j = 25 c 0.84 1.2 v t j = 125 c 0.71 reverse recovery time t rr v gs = 0 v, dis/dt = 100 a/ s, i s = 20 a 38 ns charge time ta 28 discharge time tb 10 reverse recovery charge q rr 59 nc 4. pulse test: pulse width 300 s, duty cycle 2%. 5. switching characteristics are independent of operating junction temperatures.
nvd6824nl http://onsemi.com 3 typical characteristics figure 1. on ? region characteristics figure 2. transfer characteristics v ds , drain ? to ? source (v) v gs , gate ? to ? source voltage (v) 5 4 3 2 1 0 0 20 40 60 80 100 4.0 3.5 3.0 2.5 2.0 0 20 40 60 80 100 figure 3. on ? resistance vs. gate voltage figure 4. on ? resistance vs. drain current and gate voltage v gs , gate ? to ? source voltage (v) i d , drain current (a) 10 8 6 4 2 0.014 0.016 0.018 0.020 0.022 0.024 90 70 40 20 10 0.010 0.015 0.020 0.025 0.030 figure 5. on ? resistance variation with temperature figure 6. drain ? to ? source leakage current vs. voltage t j , junction temperature ( c) v ds , drain ? to ? source (v) 150 125 100 50 25 0 ? 25 ? 50 0.4 0.8 1.2 1.6 2.0 2.4 2.8 90 70 60 50 40 30 20 10 1 k 10 k 100 k i d , drain current (a) i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance (normalized) i dss , leakage (na) r ds(on) , drain ? to ? source resistance ( ) 30 50 60 80 100 75 175 80 100 v gs = 10 v t j = 25 c 4.5 v 3.8 v 3.6 v 3.4 v 3.2 v 3.0 v 2.8 v v ds 10 v t j = 25 c t j = 125 c t j = ? 55 c i d = 20 a t j = 25 c t j = 25 c v gs = 10 v v gs = 4.5 v i d = 20 a v gs = 10 v v gs = 0 v t j = 125 c t j = 150 c
nvd6824nl http://onsemi.com 4 typical characteristics c rss figure 7. capacitance variation figure 8. gate ? to ? source voltage vs. total charge v ds , drain ? to ? source voltage (v) q g , total gate charge (nc) 80 70 60 40 30 20 10 0 0 1000 2000 3000 4000 5000 70 60 50 40 30 20 10 0 0 2 4 6 8 10 figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current r g , gate resistance ( ) v sd , source ? to ? drain voltage (v) 100 10 1 10 100 1000 1.10 1.00 0.90 0.80 0.70 0.60 0 25 50 75 100 figure 11. maximum rated forward biased safe operating area v ds , drain ? to ? source voltage (v) 100 10 1 0.1 0.01 0.1 1 10 100 c, capacitance (pf) v gs , gate ? to ? source voltage (v) t, time (ns) i s , source current (a) i d , drain current (a) 50 90 100 v gs = 0 v t j = 25 c c iss c oss v ds = 80 v i d = 20 a v gs = 10 v t r t f t d(off) t d(on) v gs = 0 v t j = 25 c v gs = 10 v single pulse t c = 25 c rds(on) limit thermal limit package limit dc 10 ms 1 ms 100 s 10 s qt qgd qgs v ds = 80 v i d = 20 a t j = 25 c
nvd6824nl http://onsemi.com 5 typical characteristics figure 12. thermal response pulse time (sec) 1 0.0001 0.01 0.001 0.00001 0.000001 0.01 0.1 1 10 r(t) ( c/w) 0.1 10
nvd6824nl http://onsemi.com 6 package dimensions dpak (single gauge) case 369c issue d b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 nvd6824nl/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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